Field of the Invention
The present invention relates to an analog-to-digital (A/D) conversion circuit and an image-capturing device having the A/D conversion circuit.
Description of the Related Art
A so-called column analog-to-digital converter (ADC)-type solid-state image-capturing device in which column sections provided to correspond to pixel columns arranged in a matrix form in an image-capturing section have an A/D conversion function has been proposed. As an A/D conversion method, there are (1) a successive approximation A/D conversion method, (2) a single slope A/D conversion method, (3) a cyclic A/D conversion method, (4) a ΔΣ A/D conversion method, and the like. A column ADC-type solid-state image-capturing device providing a time-to-digital converter Single Slope (tdcSS)-type ADC circuit, to which an A/D conversion method other than the above is applied, in column sections has been proposed (for example, see Japanese Unexamined Patent Application, First Publication No. 2011-250009). In this proposal, it is disclosed that A/D conversion can be performed on a signal from a pixel at a high signal/noise (S/N) ratio relatively easily using the tdcSS-type ADC circuit.
FIG. 7 shows an example of a configuration of a tdcSS-type ADC circuit pertaining to an existing example. The tdcSS-type ADC circuit shown in FIG. 7 has a clock generation section 1018, a reference signal generation section 1019, a count section 1103, a latch section 1108, and a comparison section 1109.
The reference signal generation section 1019 generates a ramp wave whose voltage value increases or decreases over time. The clock generation section 1018 has a delay section 1021 which has an oscillation circuit configured with a plurality of delay units and outputs a lower phase signal composed of clocks CK[0] to CK[16] output from the plurality of delay units based on a start pulse StartP, and a constant current source 1022 which supplies current for driving a delay section based on a bias voltage Vbias.
The comparison section 1109 has a first input terminal IN1 to which an analog signal Vin that is a target of A/D conversion, a second input terminal IN2 to which the ramp wave from the reference signal generation section 1019 is input, and an output terminal OUT which outputs a comparison result between the analog signal Vin and the ramp wave. The comparison section 1109 compares the analog signal Vin and the ramp wave, and ends the comparison process at a timing at which the ramp wave satisfies a predetermined condition for the analog signal Vin. The latch section 1108 latches the logic state of the lower phase signal from the clock generation section 1018 at a timing at which the comparison process in the comparison section 1109 ends. The count section 1103 performs a count using one of the clocks CK[0] to CK[16] constituting the lower phase signal from the clock generation section 1018 as a count clock, obtaining a count value.
A time in which the comparison section 1109 compares the ramp wave and the analog signal Vin is a time in accordance with a voltage value of the analog signal Vin, and a result of measuring this time is obtained as data of the lower phase signal latched by the latch section 1108 and result data of the count performed by the count section 1103. For example, by binarizing these data, it is possible to obtain digital data that is an A/D conversion result.
Next, the clock generation section 1018 is described. As the clock generation section 1018 of the tdcSS-type ADC circuit, it is preferable to use a ring delay circuit, such as a voltage controlled oscillator (VCO) circuit and the like. FIG. 8 shows an example of a configuration of the clock generation section 1018. The clock generation section 1018 has a delay section 1021 and constant current sources 1022a and 1022b. The constant current sources 1022a and 1022b correspond to the constant current source 1022 of FIG. 7.
The delay section 1021 has an oscillation circuit in which 17 delay units DU[0] to DU[16] are connected in a ring shape. The start pulse StartP is applied to a one-side input terminal of the delay unit DU[0], and the clock CK[16] from the delay unit DU[16] is input to the other-side input terminal. A voltage from a voltage source VDD is input to one-side input terminals of the delay unit DU[1] to the delay unit DU[15], and clocks from delay units of previous stages are input to the other-side input terminals. During an operation time period of the tdcSS-type ADC circuit, the voltage of the voltage source VDD is set to a high level. The clock CK[13] from the delay unit DU[13] is input to the one-side input terminal of the delay unit DU[16], and the clock CK[15] from the delay unit DU[15] of the previous stage is input to the other-side input terminal. The clock CK[13] from the delay unit DU[13] is input to the delay unit DU[16] after three stages as well as the delay unit DU[14] after one stage.
FIG. 9 shows waveforms of the start pulse StartP and output signals (clock CK[0] to CK[16]) of the delay section 1021. The horizontal direction of FIG. 9 represents time, and the vertical direction represents signal voltage. The logic state of the start pulse StartP input to the delay unit DU[0] of the first stage changes from a low (L) state to a high (H) state, so that the delay units DU[0] to DU[16] start a transition operation. At a timing at which a delay time tdly[sec] of the delay unit DU[0] elapses after the logic state of the start pulse StartP is changed, the logic state of the clock CK[0] output from the delay unit DU[0] is changed from the H stale to the L state. Subsequently, at a timing at which the delay time tdly[sec] of the delay unit DU[1] elapses after the logic state of the clock CK[0] is changed, the logic state of the clock CK[1] output from the delay unit DU[1] is changed from the L state to the H state. After that, the logic states of clocks output from respective delay units are changed in sequence in the same way.
The constant current sources 1022a and 1022b cause a constant current for driving the delay units DU[0] to DU[16] to flow. The current values of the constant current sources 1022a and 1022b are n times the current value of a unit current source that is, n×I [A] (n: a coefficient greater than 0, I: the current value of a unit current source). The current value of the unit current source is controlled by the bias voltage Vbias.
The delay section 1021 operates at a predetermined frequency which is in accordance with the delay time tdly[sec] of the delay units DU[*] (*: 0 to 16). The delay time tdly[sec] of the delay units DU[*] (*: 0 to 16) is changed in accordance with the current value n×I [A] flowing through the delay units DU[*] (*: 0 to 16). Specifically an operating frequency freq. [Hz] of the delay section 1021 is changed in accordance with the current value n×I [A] of the constant current sources 1022a and 1022b. The operating frequency freq, [Hz] is controlled to increase in approximate proportion to an increase in the current value when the current value increases within a predetermined current value range, and to decrease in approximate proportion to a decrease in the current value when the current value decreases. In other words, within the predetermined current value range, it is possible to obtain a relationship in which the current value n×I [A] and the operating frequency freq. [Hz] are approximately proportional to each other.
Equation (1) represents the operating frequency freq. [Hz] of the delay section 1021. Here, N is the number of delay units constituting the delay section 1021, tdly is the delay time of the delay units, k is a coefficient, CL is a load capacity, and Vdd is a power supply voltage.
                                                                        freq                .                            =                            ⁢                              1                                  N                  ×                                      t                    dly                                                                                                                          =                            ⁢                              k                ×                                                                            n                      ×                      I                                                              N                      ×                                              C                        L                                            ×                      Vdd                                                        ⁡                                      [                    Hz                    ]                                                                                                          (        1        )            
FIG. 10 shows a relationship between the current value n×I [A] and the operating frequency freq. [Hz] in accordance with Equation (1). The horizontal direction of FIG. 10 represents the current value n×I [A], and the vertical direction represents the operating frequency freq. [Hz]. In a predetermined current range, the operating frequency freq. [Hz] is approximately proportional to the current value n×I [A].